1. Field of the Invention
This invention relates to an input circuit (IC) used, for example, when converting a TTL-level or CMOS-level input signal into an ECL-level signal.
2. Description of the Related Art
FIG. 2 illustrates a circuit (IC) for converting a TTL-level or CMOS-level input signal into an ECL-level signal.
A signal from an output driver of a CMOS circuit or a TTL circuit is input to input terminal 2, and is supplied to the base of transistor Q3 via resistor R4. A reference voltage V.sub.R is input to the base of transistor Q3 via a low impedance voltage follower 1 and resistor R3. The value of reference voltage V.sub.R is reduced by a predetermined voltage value by resistor R7 and constant-current source I.sub.1, and the resultant voltage at the common connection of R7 and I.sub.1 is applied to the base of transistor Q4.
The emitters of transistors Q3 and Q4 are connected together and to constant-current source I3. The collector of transistor Q3 and the collector of transistor Q4 are connected to power supply terminal V.sub.cc via resistors R5 and R6, respectively, and are labelled as negative-phase output terminal Q and positive-phase output terminal Q, respectively.
FIG. 4 is a terminal-voltage diagram illustrating input signals at input terminal 2 and changes in the voltage at the base of transistor Q3 in accordance with the input signals. In FIG. 4, (a) illustrates the voltage range of an input signal from a CMOS circuit. If the power supply voltage V.sub.cc is assumed to be 5V, the (High) H level is guaranteed to be in the range of 4-5V, and the (Low) L level is guaranteed to be in the range of 0-1V.
In FIG. 4, (c) illustrates the voltage range of an input signal from a TTL circuit. The H level is guaranteed to be in the range of 2-3.5V, and the L level is guaranteed to be in the range of 0.2-0.4V.
In a level comparator comprising transistors Q3 and Q4, the base voltage of transistor Q3 must be maintained at least at .+-.4 VT (VT equals kT/g, where k is the Boltzmann constant, T is the absolute temperature, and q is the electric charge of an electron) compared with the base voltage of transistor Q4, serving as a reference voltage, for any H-level and L-level input conditions. In consideration of high-temperature operations, at least .+-.150 mv must be maintained. That is, it is necessary that when the CMOS level equals 1V (at the maximum value of the L level), the base voltage of transistor Q3--the base voltage of transistor Q4&lt;-0.15V, and when the TTL level equals 2V (at the minimum value of the H level), the base voltage of transistor Q3--the base voltage of transistor Q4&gt;0.15V.
If, for example, the reference voltage V.sub.4 is set to 2.9 V, and the value of R4/R3 is set to 2, the base voltage of transistor Q3 for CMOS and TTL input levels is converted into values shown in FIG. 4 at (b) and (d), respectively. In this case, the base voltage of transistor Q3 is about 2.27V when the CMOS level equals 1V, and is 2.6V when the TTL level equals 2V. Since the difference between the two values exceeds 0.3V, the above-described conditions are satisfied. If the values of resistor R7 and constant current source I1 are set so that the base voltage of transistor Q4 is about 2.435V (that is, V.sub.R (=2.9)-I1.times.R7=2.435V), the input circuit shown in FIG. 2 outputs input signals from the CMOS circuit and the TTL circuit to positive-phase output terminal Q and negative-phase output terminal Q as differential ECL signals. The base voltage of transistor Q3 becomes 2.4V at an ordinary threshold level 1.4V of a TTL signal. Since this value is very close to the threshold level of the input circuit shown in FIG. 2, this case has desirable characteristics.
The conventional input circuit shown in FIG. 2, however, has problems particularly due to a parasitic capacitance C.sub.x present, for example, in constant current source I3. The problems will be discussed below with reference to FIGS. 3(a)-3(d).
FIG. 3(a) illustrates the waveform of the signal input to input terminal 2 and the base of transistor Q3. FIGS. 3(b) and 3(c) illustrate negative-phase and positive-phase ECL output signals from the collector of transistor Q3 and the collector of transistor Q4, respectively.
The emitter voltage of transistors Q3 and Q4 is V.sub.R -R7.multidot.I1-V.sub.f (V.sub.f is the base-emitter drop voltage when the transistor is turned on) before time t.sub.1, and the discharging operation of parasitic capacitance C.sub.x has been completed.
When the input signal has changed from the L level to the H level at time t.sub.1, the base-emitter voltage of transistor Q3 has a large value instantaneously. Hence, as shown in FIG. 3(b), a negative overshoot is generated at the collector of transistor Q3. On the other hand, transistor Q4 is not immediately turned off at time t.sub.1, and the collector voltage of transistor Q4 gradually increases as the parasitic capacity C.sub.x is charged. When the H level of the input signal equals 5V, parasitic capacity C.sub.x is charged until the emitter voltage of transistor Q3 becomes 3.6-V.sub.f.
Since the input signal changes from the H level to the L level at time t.sub.2, transistor Q3 is turned off, and the collector voltage of transistor Q3 changes from the L level to the H level (FIG. 3(b)). However, transistor Q4 is not turned on until the discharging operation of parasitic capacity C.sub.x by constant current source I3 is completed. Hence, the collector voltage of transistor Q4 changes to the L level at a time t.sub.3, at which time the discharging operation has been completed (FIG. 3(c)). This discharging operation continues until the emitter voltage of transistor Q4 becomes V.sub.R -R7.multidot.I1-V.sub.f.
In the above-described differential ECL output signals, when the input signal changes from the H level to the L level, a period of time (from t.sub.2 to t.sub.3) exists during which the logic level of each of the signals Q and Q assumes the H level. During this period, as shown in FIG. 3(d), a noise pulse may be generated or the pulse duty ratio may be deteriorated in the ECL circuit of the following stage. Particularly when the input signal is a clock signal, fatal problems will, in many cases, occur. In order to overcome such problems, a circuit having a time constant has conventionally been used for suppressing the generation of the noise pulse, thereby causing a decrease in the permissible highest value of the frequency of the input signal.